Conventionally, an analog to digital converter (ADC) is provided for converting an analog signal from a sensor and an antenna to a digital signal in various types of electronic apparatuses for measuring and performing wireless communication. There are various types of ADCs, but a successive approximation type ADC is widely used because of its small power consumption and circuit scale.
This successive approximation type ADC is generally provided with a comparator, a plurality of capacitors connected in parallel to the comparator, a voltage conversion circuit which supplies a voltage to the capacitors, and a logic circuit which controls operation of the voltage conversion circuit (refer to, for example, Patent Document 1). For example, a complementary MOS (CMOS) inverter is used as the voltage conversion circuit. In the successive approximation type ADC, the logic circuit inputs a high level or low level control signal to each of the voltage conversion circuits (CMOS inverters) on the basis of the comparison result of the comparator. On the basis of the control signal, the CMOS inverter supplies either a source potential (high level) of a P-type transistor or a source potential (low level) of an N-type transistor to the capacitor. Then, the comparator performs comparison a plurality of times, and outputs a digital signal including comparison results thereof as a result of AD conversion.
In such successive approximation type ADC, when an input of a very small analog signal is assumed, in order to convert the minute analog signal with a high degree of accuracy, it is necessary to improve resolution of the ADC. This resolution is ability indicating how fine a unit in which the ADC may convert the analog signal. In general, the resolution is represented by a value obtained by dividing an input range being a range of the analog signal on which the AD conversion may be performed by 2m (m is the number of bits of the digital signal), and the smaller the value, the higher the resolution. Therefore, if m is constant, the narrower the input range, the smaller the value obtained by dividing the input range by 2m (that is, the resolution improves). Herein, when increasing a held voltage of the capacitor in the ADC having the configuration described above, the CMOS inverter supplies the source potential (high level) of the P-type transistor to the capacitor. On the other hand, when decreasing the held voltage of the capacitor, the CMOS inverter supplies the source potential (low level) of the N-type transistor to the capacitor. Since the ADC may perform the AD conversion on the analog signal within the range of fluctuation of the held voltage, the range of the fluctuation corresponds to the input range of the ADC. Assuming that the low level is constant, this input range becomes narrower as the high level (that is, the source potential of the P-type transistor) supplied to the capacitor is lower. Therefore, as the source potential is lowered, the resolution is improved.